ASoC: dt-bindings: fsl_spdif: Add two PLL clock source

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Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Shengjiu Wang 2022-07-01 17:32:40 +08:00 • committed by Mark Brown

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Documentation/devicetree/bindings/sound/fsl,spdif.yaml

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