Amlogic clock updates for v6.3

* Use .determine_rate() instead of .round_rate() for the dualdiv, mpll,
   sclk-div and cpu-dyn-div amlogic clock drivers.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmPOlBQACgkQ5vwPHDfy
 2oUu5hAAlu9pf4fmkUpPFyFy9lmz5k2xUzNYkluRBcfzPjZl+1ju8HcuWkXmJI3/
 r4GmgWajVMycVXhXX/1eqK1matB9aEfgf38UOMrvc8ytRsdPGAY7cRCDIhHXS/a8
 n/PhlCdEoMAN4V2rqPUvRboMBkbehs0q6Qj0TnUQEdHUoKDZol8R2N0+HvhTZz2r
 fL9jTAjMEcp78eDsked1hxBjZ42aRxQy8KqC5ecU28EhmUnXgAG90TLgc/BMiD7g
 QlIns/H77ozoHAXty2n7/FL3Zq84fT4kKdSAjjn1iPa2KEQyVfYhv3bjVlfDm2n5
 mya+ne6MJqZpXLP9FsvAKLeSKKG3n707XdgLM3f6wUZD0VhYFwbswo+BOEaB4rCl
 7Gs4Uv/e55YTOzSKBkuuvRY2UaGBVq2eUO9f0tx/h6nN0SzxnwYKDDPCj0+2iZHX
 tKdiC0KtxJm74OqdhQPdPPB+JNt0dvwj2WsgKu6wwaTLl71c3pf7FgZGpucsw+eR
 e/IsDkaJhcmDEq4b1NpxNS/kHP6rLfHG3ZQE+N65Mo8wYnTtI3CiOrQv2pO3ieqn
 oPtR/IVtDxw6o+M1h0bjkuBwM3VwpbglnyQSh5xnETjSYLRcQL1lItl3oB9lkt97
 IoeGqkceJ7Y3rOCiLyZxqc2hZtmba6fkT6uUvhFwqaHixiqi0L0=
 =mb3L
 -----END PGP SIGNATURE-----

Merge tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk updates from Jerome Brunet:

 - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll,
   sclk-div and cpu-dyn-div amlogic clock drivers

* tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
  clk: meson: sclk-div: switch from .round_rate to .determine_rate
  clk: meson: dualdiv: switch from .round_rate to .determine_rate
  clk: meson: mpll: Switch from .round_rate to .determine_rate
This commit is contained in:
Stephen Boyd 2023-01-25 11:31:13 -08:00
commit df43ce489d
4 changed files with 36 additions and 25 deletions