drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence

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Plug bxt PLL code into existing shared DPLL framework.

v2: (imre)
- squash in Satheeshakrishna's "Define BXT clock registers" and
  "Add state variables for bxt clock registers" patches
- squash in Vandanas's "Change grp access to lane access for PLL"
- fix group vs. lane access in bxt_ddi_pll_get_hw_state
- add code comment why we read from lane registers while writing to
  group registers
- clean up register macros
- use BXT_PORT_PLL_* macros instead of open-coding the same
- check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23
  during hardware state readout
- add missing LANESTAGGER_STRAP_OVRD masking
- add note about missing step according to the latest BUN for
  PORT_PLL_9/lockthresh

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Satheeshakrishna M 2014-08-22 09:49:09 +05:30 • committed by Daniel Vetter

parent ff6d9f55fe

commit dfb8240847

3 changed files with 244 additions and 0 deletions

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3

drivers/gpu/drm/i915/i915_drv.h

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76

drivers/gpu/drm/i915/i915_reg.h

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165

drivers/gpu/drm/i915/intel_ddi.c

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