clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

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If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.

The previous code never handled the parent mux if there was a
bypass_reg.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Dinh Nguyen 2021-06-10 21:52:01 -05:00 • committed by Stephen Boyd

parent c2c9c5661a

commit dfd1427c37

1 changed files with 8 additions and 3 deletions

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drivers/clk/socfpga/clk-periph-s10.c

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