perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask

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Stephane pointed out that the extrareg mask was one bit too short.
The bubble width field was truncated by one bit. Fix that here.
Also add some extra comments on the reserved bits inside the event
select code.

Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1441835640-21347-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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Andi Kleen 2015-09-09 14:54:00 -07:00 • committed by Ingo Molnar

parent d0dc8494cd

commit dfe1f3cb31

1 changed files with 5 additions and 1 deletions

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arch/x86/kernel/cpu/perf_event_intel.c

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