drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b

Browse source

There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.

v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper

Bspec: 54128
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com

...

This commit is contained in:

Jani Nikula 2021-09-09 15:52:04 +03:00

parent 652135940e

commit e01163e82b

1 changed files with 11 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

11

drivers/gpu/drm/i915/display/intel_dp_mst.c

View file