clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers

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Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-05-13 16:46:34 +01:00 • committed by Geert Uytterhoeven

parent d3c25dd161

commit e018f9f897

1 changed files with 20 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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