riscv: errata: Add Andes alternative ports

Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2026-09-26 18:16:26 +00:00 · 2023-08-18 14:57:19 +01:00 · 2023-08-18 14:57:19 +01:00 · e021ae7f51
commit e021ae7f51
parent d6ca3a56f4
7 changed files with 102 additions and 0 deletions
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
--- a/arch/riscv/errata/andes/Makefile
+++ b/arch/riscv/errata/andes/Makefile
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c