drm/vc4: dsi: Correct DSI register definition

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The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
definitions were swapped, so trying to use more than a single data
lane failed as lane 1 would get powered down.
(In theory a 4 lane device would work as all lanes would remain
powered).

Correct the definitions.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-3-maxime@cerno.tech

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Dave Stevenson 2020-12-03 14:25:37 +01:00 • committed by Maxime Ripard

parent 51f4fcd9c4

commit e02d5c43f2

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drivers/gpu/drm/vc4/vc4_dsi.c

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