drm/amdgpu: Hardcode reg access using L1 security

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Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
default as the non-security VF will no longer be supported.

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Trigger Huang 2019-06-03 16:48:17 +08:00 • committed by Alex Deucher

parent e038b9016a

commit e0301317ac

1 changed files with 6 additions and 9 deletions

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15

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

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