drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset

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On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

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AngeloGioacchino Del Regno 2021-01-12 20:26:26 +01:00 • committed by Rob Clark

parent 3f2bc3856b

commit e0485f1d04

1 changed files with 5 additions and 4 deletions

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drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

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