clk: pistachio: Lock the PLL when enabled upon rate change

Browse source

Currently, when the rate is changed, the driver makes sure the
PLL is enabled before doing so. This is done because the PLL
cannot be locked while disabled. Once locked, the drivers
returns the PLL to its previous enable/disable state.

This is a bit cumbersome, and can be simplified.

This commit reworks the .set_rate() functions for the integer
and fractional PLLs. Upon rate change, the PLL is now locked
only if it's already enabled.

Also, the driver locks the PLL on .enable(). This makes sure
the PLL is locked when enabled, and not locked when disabled.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

...

This commit is contained in:

Ezequiel Garcia 2015-05-26 19:01:08 -03:00 • committed by Stephen Boyd

parent 4f4adfbf8e

commit e0b7a79524

1 changed files with 10 additions and 18 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

28

drivers/clk/pistachio/clk-pll.c

View file