clk: samsung: exynos990: Fix PERIC0/1 USI clock types

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Use nMUX() for USI and UART user muxes to allow reparenting between
OSC and CMU IP output when changing rates, and use DIV_F() with
CLK_SET_RATE_PARENT on their dividers and gates so rate requests
propagate upward.

Consolidate identical USI parent arrays into shared
mout_peric0_nonbususer_p and mout_peric1_nonbususer_p.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://patch.msgid.link/20260528-perics-usi-v1-1-13a6ee4d1a6f@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

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Denzeel Oliva 2026-05-28 15:09:01 -05:00 • committed by Krzysztof Kozlowski

parent 44984aaf1a

commit e11560b050

1 changed files with 143 additions and 164 deletions

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drivers/clk/samsung/clk-exynos990.c

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