drm/i915/gvt: Align render mmio list to cacheline

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Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

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Changbin Du 2017-04-06 10:55:02 +08:00 • committed by Zhenyu Wang

parent 0b063bd3ea

commit e1236bc06c

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/i915/gvt/render.c

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