clk: rockchip: add a dummy clock for the watchdog pclk on rk3288

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The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Heiko Stuebner 2015-01-20 21:06:55 +01:00

parent cc6430689e

commit e142a4e914

1 changed files with 8 additions and 0 deletions

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drivers/clk/rockchip/clk-rk3288.c

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