Allwinner clock changes for 4.20

Our usual set of changes for the Allwinner SoCs clock support. The most notable changes are: - A bunch of changes and fixes to support the A64 display engine - Some fixes to support the A83t display engine -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAluvk1oACgkQ0rTAlCFN r3SbPA//dGLuD23yNl0KeE4GKUnE68MyZy1FAiDXW805VDMBrdPrIxoYMQljsor7 5jnFOGQfo9oEghO/7Pew5uI2Ky4xIYSeDWmPh/7kcIunVy0oVAx33h35KAZ08qpH IRFIFZieX8LiXAr4j9MDGWQnaO9EbP39FKeHy5wz9hY8DsfgAL1lOgIsmohpVOvm o3X5/Z/3OEwc/0Wi0+sxS9/dGiQjv/7HDHJB2DaCsPPtWM6yxIFA/D2qLbu8O76/ 3R69IMgctn/afBmeh6nVh9odfjzLxbFXhuKqFxjD4O93/vzQr93/WRHNghxUuoAG KEHWn+btIMXmNAtdBHmdJDS5Upg/UzY7uN5WZ6csnCKs4oLYfZvdaOQ1F5HMmJqT 6gMqZuqs8xhAozNHnBWNwjH11gctqQh13InhQYcGJE1IFiIdNN1ZCpL/XSUuPEfW cKqK3/g1EQ62S3sAbLmkD9xPd1D/p48pHkUqg1jIIkEvfI/T4bbgD7NIuBieRFZ4 cDT7H2f1dzNzyNiwfAoPVUQJm4y/EtastqJSvL/Jaw+hc+2Bvi1SRI16xsUzZILe l2tkk3qLY1CoITa2jnemHuGRuSWLhylg4Ypw5pK3LyMl6TP3df4rFQpnHwLaOxK6 ghRV9AVis2mjjRxkKuycTBIXmvyihmFr44gVYsXkqQH/HNtIOr4= =rcxu -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull allwinner clock changes from Maxime Ripard: Our usual set of changes for the Allwinner SoCs clock support. The most notable changes are: - A bunch of changes and fixes to support the A64 display engine - Some fixes to support the A83t display engine * tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position
2026-11-10 20:48:12 +00:00 · 2018-10-01 14:57:43 -07:00 · 2018-10-01 14:57:43 -07:00 · e15d598b5c
commit e15d598b5c
parent 5b394b2ddf 8b2a378704
11 changed files with 144 additions and 86 deletions
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h