staging: rtl8723au: remove extra parentheses around right bit shift operations

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Removes extra parentheses around bitwise right shift operations.
The cases handled here are when resultant values are assigned to
variables. The issue was detected and resolved using the following
coccinelle script:

@@
expression e, e1;
constant c;
@@

e =
-(e1
+e1
>>
-c);
+c;

@@
identifier i;
constant c;
type t;
expression e;
@@

t i =
-(e
+e
>>
-c);
+c;

@@
expression e, e1;
identifier f;
constant c;
@@

e1 = f(...,
-(e
+e
>>
-c)
+c
,...);

Signed-off-by: Aya Mahfouz <mahfouz.saif.elyazal@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

This commit is contained in:

Aya Mahfouz 2015-03-04 07:34:07 +02:00 • committed by Greg Kroah-Hartman

parent 2597864233

commit e1bc88f1d9

2 changed files with 6 additions and 6 deletions

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6

drivers/staging/rtl8723au/hal/odm.c

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6

drivers/staging/rtl8723au/hal/rtl8723a_hal_init.c

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