dt-bindings: PCI: xilinx-cpm: Fix reg property order

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All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.

This order is also suggested by node name which is pcie@fca10000 which
suggests that cpm_slcr register should be the first.

Driver itself is using devm_platform_ioremap_resource_byname() for both
names that's why there is no functional change even on description which
are using current order.

But still prefer to change order to cover currently used description.
Fixes: e22fadb1d0 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220516102217.25960-1-bharat.kumar.gogada@xilinx.com

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Bharat Kumar Gogada 2022-05-16 15:52:17 +05:30 • committed by Rob Herring

parent 0a1e19c8a6

commit e2c6170a55

1 changed files with 5 additions and 5 deletions

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Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

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