drm/amd/display: Better handling of dummy p-state table

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[Why]
Some scenarios where we use a UCLK frequency in between dummy p-state table
entries result in a p-state hang, due to the table not having a close
enough match, so the default DPM0 latency is used, which can be too long to
support dummy p-state switching in these scenarios.

[How]
 - old: match if current freq is within +- margin of table entry
 - new: find largest table entry that is lower than current freq + margin
   - lower than DPM0 will still use DPM0

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Joshua Aberback 2021-01-21 02:33:31 -05:00 • committed by Alex Deucher

parent fd952d4364

commit e2dcd9b8b8

1 changed files with 5 additions and 7 deletions

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drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

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