clk: imx: fracn-gppll: Add 333.333333 MHz support

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Some parallel panels have a pixelclk of 33.30 MHz. Add support for
333.333333 MHz so a by 10 divider can be used to derive the exact pixelclk.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260313070740.585043-2-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

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Alexander Stein 2026-03-13 08:07:31 +01:00 • committed by Abel Vesa

parent fca8688a67

commit e2f8311a6a

1 changed files with 1 additions and 0 deletions

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drivers/clk/imx/clk-fracn-gppll.c

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