mmc: sdhci_am654: Clear HISPD_ENA in some lower speed modes

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According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.

To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.

Use the sdhci writeb callback to implement this condition.

[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

...

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Faiz Abbas 2019-04-01 18:28:04 +05:30 • committed by Ulf Hansson

parent 3b407b4f3a

commit e374e87538

2 changed files with 23 additions and 0 deletions

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1

drivers/mmc/host/Kconfig

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22

drivers/mmc/host/sdhci_am654.c

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