drm/msm/a6xx: Retrieve gmu core range by index

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Some GPUs like A612 doesn't use a named register range resource. This
is because the reg-name property is discouraged when there is just a
single resource.

To address this, retrieve the 'gmu' register range by its index. It is
always guaranteed to be at index 0.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696673/
Message-ID: <20251231-qcs615-spin-2-v6-1-da87debf6883@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

...

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Akhil P Oommen 2025-12-31 14:15:22 +05:30 • committed by Rob Clark

parent dc220915dd

commit e39333a81e

1 changed files with 6 additions and 8 deletions

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drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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