irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}

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On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
bits is ignored.

Use bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL
and then update the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK for
supporting both SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20250224131253.134199-12-biju.das.jz@bp.renesas.com

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Biju Das 2025-02-24 13:11:27 +00:00 • committed by Thomas Gleixner

parent 76c3b77473

commit e3a16c33db

1 changed files with 9 additions and 4 deletions

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drivers/irqchip/irq-renesas-rzv2h.c

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