clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc

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Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50%  duty
cycle, divfree50 can generate clock of 50% duty cycle even in odd
value divisor.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917081903.25139-2-heiko@sntech.de

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Finley Xiao 2019-09-17 10:19:00 +02:00 • committed by Heiko Stuebner

parent 762539d699

commit e40781098f

1 changed files with 40 additions and 4 deletions

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drivers/clk/rockchip/clk-px30.c

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