drm/i915: implement the Haswell mode set sequence workaround

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This workaround is described in the mode set sequence documentation.
When enabling planes for the second pipe, we need to wait for 2
vblanks on the first pipe. This should solve "a flash of screen
corruption if planes are enabled on second/third pipe during the time
that big FIFO mode is exiting". Watermarks are fun :)

v2: Save indentation levels

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Paulo Zanoni 2013-09-20 16:21:19 -03:00 • committed by Daniel Vetter

parent dda9a66a81

commit e4916946b8

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drivers/gpu/drm/i915/intel_display.c

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