drm/i915: Add an interface to dynamically change the cache level

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[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]

[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Chris Wilson 2011-04-04 09:44:39 +01:00 • committed by Keith Packard

parent d5bd144959

commit e4ffd173a1

4 changed files with 71 additions and 7 deletions

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5

drivers/gpu/drm/i915/i915_drv.h

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60

drivers/gpu/drm/i915/i915_gem.c

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7

drivers/gpu/drm/i915/i915_gem_gtt.c

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6

drivers/gpu/drm/i915/intel_ringbuffer.c

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