clk: renesas: r9a09g011: Add PFC clock and reset entries

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Add PFC clock/reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Phil Edworthy 2022-05-18 14:52:08 +01:00 • committed by Geert Uytterhoeven

parent b6ee0bbf38

commit e55c4481e7

1 changed files with 2 additions and 0 deletions

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drivers/clk/renesas/r9a09g011-cpg.c

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