drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

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The spreadsheet defines the PLL register block as having
the dwords in the following order:

block   dwords    offsets
PLL1    0x0-0x7   0x00-0x1f
PLL2    0x0-0x7   0x20-0x3f
PLL1ext 0x10-0x1f 0x40-0x5f
PLL2ext 0x10-0x1f 0x60-0x7f

So dword indexes 0x8-0xf don't even exist. Renumber
our register defines to match.

Note that the spreadsheet used hex numbering whereas our
defiens are in decimal. Perhaps we should change that?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240422083457.23815-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

...

This commit is contained in:

Ville Syrjälä 2024-04-22 11:34:47 +03:00

parent a39eec1975

commit e55f8dfa35

2 changed files with 21 additions and 21 deletions

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18

drivers/gpu/drm/i915/display/intel_dpll.c

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24

drivers/gpu/drm/i915/i915_reg.h

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