net/mlx5: DR, Cache STE shadow memory

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During rule insertion on each ICM memory chunk we also allocate shadow memory
used for management. This includes the hw_ste, dr_ste and miss list per entry.
Since the scale of these allocations is large we noticed a performance hiccup
that happens once malloc and free are stressed.
In extreme usecases when ~1M chunks are freed at once, it might take up to 40
seconds to complete this, up to the point the kernel sees this as self-detected
stall on CPU:

 rcu: INFO: rcu_sched self-detected stall on CPU

To resolve this we will increase the reuse of shadow memory.
Doing this we see that a time in the aforementioned usecase dropped from ~40
seconds to ~8-10 seconds.

Fixes: 29cf8febd1 ("net/mlx5: DR, ICM pool memory allocator")
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

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Yevgeny Kliteynik 2021-12-24 01:07:30 +02:00 • committed by Saeed Mahameed

parent f908a35b22

commit e5b2bc30c2

2 changed files with 79 additions and 35 deletions

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109

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_icm_pool.c

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5

drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h

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