iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

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Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.

SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY,
since resource size can be either 64k/128k.
For this, arm_smmu_device_dt_probe/acpi_probe has been moved before
platform_get_resource call, so that SMMU options are set beforehand.

Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Linu Cherian 2017-06-22 17:35:37 +05:30 • committed by Will Deacon

parent 403e8c7c5b

commit e5b829de05

3 changed files with 57 additions and 18 deletions

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1

Documentation/arm64/silicon-errata.txt

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6

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

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68

drivers/iommu/arm-smmu-v3.c

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