drm/i915: s/pch_pll/shared_dpll/

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For fastboot we need some support to read out the sharing state of
plls, at least for platforms where they can be shared (or freely
assigned at least). Now for ivb we already have pretty extensive
infrastructure for tracking pch plls, and it took us an aweful lot of
tries to get that remotely right. Note that hsw could also share plls,
but even now they're already freely assignable. So we need this on
more than just ivb.

So on top of the usual fastboot fun pll sharing seems to be an
additional step up in fragility. Hence a common infrastructure for all
shared/freely assignable display plls seems to be in order.

The plan is to have a bit of dpll hw state readout code, which can be
used individually, but also to fill in the pipe config. The hw state
cross check code will then use that information to make sure that
after every modeset every pipe still is connected to a pll which still
has the correct configuration - a lot of the pch pll sharing bugs
where due to incorrect sharing.

We start this endeavour with a simple s/pch_pll/shared_dpll/ rename
job.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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This commit is contained in:

Daniel Vetter 2013-06-05 13:34:06 +02:00

parent f4a091c71b

commit e72f9fbf99

4 changed files with 67 additions and 67 deletions

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14

drivers/gpu/drm/i915/i915_drv.c

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6

drivers/gpu/drm/i915/i915_drv.h

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112

drivers/gpu/drm/i915/intel_display.c

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2

drivers/gpu/drm/i915/intel_drv.h

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