From e806c63ba51a70aa8e19f749eb36b4d81760f705 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 12:32:37 +0200 Subject: [PATCH] arm64: dts: qcom: Rename pci@ nodes to pcie@ PCIe hosts/devices commonly use the 'pcie' for their node name to reflect they're not legacy PCI. Every couple months someone comes around to clean this up because people keep introducing new uses of 'pci@'. Seems like it's my turn now, so do that for RCs and the downstream devices (switches etc.) defined in board files. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260701-topic-dts_pci_pcie-v1-1-aab8de213b39@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/hamoa.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 4 ++-- arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++-- .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 8 ++++---- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- 9 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 6356f977f720..72c23aef1207 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2827,7 +2827,7 @@ #interconnect-cells = <2>; }; - pcie4: pci@1bf0000 { + pcie4: pcie@1bf0000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01bf0000 0x0 0x3000>, @@ -3043,7 +3043,7 @@ status = "disabled"; }; - pcie5: pci@1b40000 { + pcie5: pcie@1b40000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b40000 0x0 0x3000>, @@ -3315,7 +3315,7 @@ status = "disabled"; }; - pcie6: pci@1c00000 { + pcie6: pcie@1c00000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -3531,7 +3531,7 @@ status = "disabled"; }; - pcie3b: pci@1b80000 { + pcie3b: pcie@1b80000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b80000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 09527dcf9576..86168e445340 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3404,7 +3404,7 @@ status = "disabled"; }; - pcie6a: pci@1bf8000 { + pcie6a: pcie@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01bf8000 0 0x3000>, @@ -3547,7 +3547,7 @@ status = "disabled"; }; - pcie5: pci@1c00000 { + pcie5: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c00000 0 0x3000>, @@ -3684,7 +3684,7 @@ status = "disabled"; }; - pcie4: pci@1c08000 { + pcie4: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c08000 0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 44bd9b1a1765..4fc5f482a18f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -271,7 +271,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -279,7 +279,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index d1346ca5dd4e..299d0da15a15 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -421,7 +421,7 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pci@0,0 { + pcie@0,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -429,7 +429,7 @@ ranges; reg = <0x010000 0x00 0x00 0x00 0x00>; - pci@2,0 { + pcie@2,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index e6beb4393430..77c28c19d17a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -117,7 +117,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -125,7 +125,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index efe1e74fe509..a2daef463c3d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2256,7 +2256,7 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -2435,7 +2435,7 @@ status = "disabled"; }; - pcie1: pci@1c10000 { + pcie1: pcie@1c10000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 83908db335af..937b63eae3ba 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,7 +130,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -138,7 +138,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -225,7 +225,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -233,7 +233,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e9a932c90d14..1acbfe7baa13 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -954,7 +954,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -962,7 +962,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index c8eed8ba93f5..4f6932dd1139 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -790,7 +790,7 @@ ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -798,7 +798,7 @@ ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>;