drm/xe/xe3p_xpc: XeCore mask spans four registers

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On Xe3p_XPC, there are now four registers reserved to express the XeCore
mask rather than just three. Define the new registers and update the IP
descriptor accordingly.

Note that this only applies to Xe3p_XPC for now; Xe3p_LPG still only
uses three registers to express the mask.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260205214139.48515-4-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

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This commit is contained in:

Matt Roper 2026-02-05 13:41:41 -08:00

parent 6acf3d3ed6

commit e8100643ff

4 changed files with 7 additions and 3 deletions

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2

drivers/gpu/drm/xe/regs/xe_gt_regs.h

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2

drivers/gpu/drm/xe/xe_gt_topology.c

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2

drivers/gpu/drm/xe/xe_gt_types.h

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4

drivers/gpu/drm/xe/xe_pci.c

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