drm/xe/mcr: Add L3BANK steering for DG2

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Some register ranges with replication type L3BANK were missing from the
driver table. The following warning was triggering when adding a
workaround touching the register 0xb188:

	xe 0000:03:00.0: Did not find MCR register 0xb188 in any MCR steering table

Add the L3BANK ranges according to the spec.

v2:
  - Fix typo in one of the ranges: s/0x00BCFF/0x008CFF/ (Matt Roper)
  - Add termination rule in the init function for L3BANK (Matt Roper)

Bspec: 66534
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

...

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Lucas De Marchi 2023-03-06 16:40:27 -08:00 • committed by Rodrigo Vivi

parent 4b1430f775

commit e84535d860

1 changed files with 19 additions and 0 deletions

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drivers/gpu/drm/xe/xe_gt_mcr.c

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