clk: imx8mn: Define gates for pll1/2 fixed dividers

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On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Leonard Crestez 2019-10-16 11:57:40 +00:00 • committed by Shawn Guo

parent 3e4947acad

commit e8688fe8df

2 changed files with 56 additions and 20 deletions

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57

drivers/clk/imx/clk-imx8mn.c

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19

include/dt-bindings/clock/imx8mn-clock.h

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