drm/msm/dsi/phy: Toggle back buffer resync after preparing PLL

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[ Upstream commit b63f008f39 ]

According to Hardware Programming Guide for DSI PHY, the retime buffer
resync should be done after PLL clock users (byte_clk and intf_byte_clk)
are enabled.  Downstream also does it as part of configuring the PLL.

Driver was only turning off the resync FIFO buffer, but never bringing it
on again.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/657823/
Link: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-6-ee633e3ddbff@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

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Krzysztof Kozlowski 2025-06-10 16:05:44 +02:00 • committed by Greg Kroah-Hartman

parent 2c55ec1506

commit e8b63d342d

1 changed files with 4 additions and 0 deletions

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drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

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