ARM: vexpress/dcscb: fix cache disabling sequences

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Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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Nicolas Pitre 2013-07-16 20:59:53 -04:00

parent 3b2f64d00c

commit e8f9bb1bd6

1 changed files with 37 additions and 21 deletions

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arch/arm/mach-vexpress/dcscb.c

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