perf/x86: Add config_mask to represent EVENTSEL bitmask

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Different vendors may support different fields in EVENTSEL MSR, such as
Intel would introduce new fields umask2 and eq bits in EVENTSEL MSR
since Perfmon version 6. However, a fixed mask X86_RAW_EVENT_MASK is
used to filter the attr.config.

Introduce a new config_mask to record the real supported EVENTSEL
bitmask.
Only apply it to the existing code now. No functional change.

Co-developed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Link: https://lkml.kernel.org/r/20240626143545.480761-7-kan.liang@linux.intel.com

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Kan Liang 2024-06-26 07:35:38 -07:00 • committed by Peter Zijlstra

parent 608f6976c3

commit e8fb5d6e76

3 changed files with 12 additions and 1 deletions

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5

arch/x86/events/core.c

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1

arch/x86/events/intel/core.c

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7

arch/x86/events/perf_event.h

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