perf: Fix LLC-* events on Intel Nehalem/Westmere

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On Intel Nehalem and Westmere CPUs the generic perf LLC-* events count the
L2 caches, not the real L3 LLC - this was inconsistent with behavior on
other CPUs.

Fixing this requires the use of the special OFFCORE_RESPONSE
events which need a separate mask register.

This has been implemented by the previous patch, now use this infrastructure
to set correct events for the LLC-* on Nehalem and Westmere.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1299119690-13991-3-git-send-email-ming.m.lin@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

This commit is contained in:

Andi Kleen 2011-03-03 10:34:48 +08:00 • committed by Ingo Molnar

parent a7e3ed1e47

commit e994d7d23a

2 changed files with 79 additions and 17 deletions

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15

arch/x86/kernel/cpu/perf_event.c

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81

arch/x86/kernel/cpu/perf_event_intel.c

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