spi: bcm2835aux: fix CPOL/CPHA setting

Browse source

The auxiliary spi supports only CPHA=0 modes as the first bit is
always output to the pin before the first clock cycle. In CPHA=1
modes the first clock edge outputs the second bit hence the slave
can never read the first bit.

Also the CPHA registers switch between clocking data in/out on
rising/falling edge hence depend on the CPOL setting.

Signed-off-by: Stephan Olbrich <stephanolbrich@gmx.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Stephan Olbrich 2016-02-14 11:04:29 +01:00 • committed by Mark Brown

parent b4e2adef62

commit e9dd4edcc9

1 changed files with 8 additions and 11 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

19

drivers/spi/spi-bcm2835aux.c

View file