clk: imx: Refactor entire sccg pll clk

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Make the entire combination of plls to be one single clock. The parents used
for bypasses are specified each as an index in the parents list.
The determine_rate does a lookup throughout all the possible combinations
for all the divs and returns the best possible 'setup' which in turn is used
by set_rate later to set up all the divs and bypasses.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Abel Vesa 2019-02-22 17:07:32 +00:00 • committed by Stephen Boyd

parent 3b9ea606cd

commit e9dda4af68

3 changed files with 417 additions and 159 deletions

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53

drivers/clk/imx/clk-imx8mq.c

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560

drivers/clk/imx/clk-sccg-pll.c

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9

drivers/clk/imx/clk.h

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