clk: tegra20: Correct PLL_C_OUT1 setup

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PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2018-01-10 16:59:43 +03:00 • committed by Thierry Reding

parent 2dcabf053c

commit ea141d5819

1 changed files with 3 additions and 3 deletions

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drivers/clk/tegra/clk-tegra20.c

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