perf/cxlpmu: Fix 64-bit write to 32-bit HDM filter register

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The HDM decoder filter configuration register is 32 bits wide, but the
driver programs it with a 64-bit writeq(). The filter value never
exceeds 32 bits, so the upper half of the write is always zero and
lands in the adjacent Filter ID 1 (Channel/Rank/Bank) configuration
register at offset+4.

Fixes: 5d7107c727 ("perf: CXL Performance Monitoring Unit driver")
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Will Deacon <will@kernel.org>

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Davidlohr Bueso 2026-07-15 12:14:52 -07:00 • committed by Will Deacon

parent 18ec1f543a

commit ea434e8fd3

1 changed files with 1 additions and 1 deletions

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drivers/perf/cxl_pmu.c

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