drm/msm/adreno: Add fenced regwrite support

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[ Upstream commit a27d774045 ]

There are some special registers which are accessible even when GX power
domain is collapsed during an IFPC sleep. Accessing these registers
wakes up GPU from power collapse and allow programming these registers
without additional handshake with GMU. This patch adds support for this
special register write sequence.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673368/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Akhil P Oommen 2025-09-08 13:57:00 +05:30 • committed by Greg Kroah-Hartman

parent 74b1cdb13f

commit ea44af1bd8

3 changed files with 90 additions and 11 deletions

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80

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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1

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

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20

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

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