clk: sunxi: Add support for table-based divider clocks

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A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2014-06-26 23:55:42 +08:00 • committed by Maxime Ripard

parent 9a5e6c7eb5

commit ea5671bffb

1 changed files with 5 additions and 4 deletions

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drivers/clk/sunxi/clk-sunxi.c

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