clk: mmp2: Stop pretending PLL outputs are constant

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The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly
off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default,
but also configurable.

Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various
values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and
set-pll2-988mhz Open Firmware words.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

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Lubomir Rintel 2020-03-09 20:42:42 +01:00 • committed by Stephen Boyd

parent 5d34d0b32d

commit ea56ad6026

1 changed files with 14 additions and 2 deletions

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drivers/clk/mmp/clk-of-mmp2.c

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