Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

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Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk

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This commit is contained in:

Michael Turquette 2015-12-22 10:12:42 -08:00

parent d90e149666 dfff24bde7

commit eaaa6fb53f

15 changed files with 2025 additions and 33 deletions

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193

include/dt-bindings/clock/rk3036-cru.h

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220

include/dt-bindings/clock/rk3228-cru.h

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4

include/dt-bindings/clock/rk3288-cru.h

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