clk: renesas: r9a09g056: Add clock and reset entries for TSU

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Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Ovidiu Panait 2025-12-09 09:11:14 +00:00 • committed by Geert Uytterhoeven

parent 2efea3b35c

commit ebb3acf4d7

1 changed files with 6 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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