clk: aspeed: Add SDIO gate

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The clock divisor comes with an enable bit (gate). This was not
implemented as we didn't have access to SD hardware when writing the
driver. Now that we can test it, add the gate as a parent to the
divisor.

There is no reason to expose the gate separately, so users will enable
it by turning on the ASPEED_CLK_SDIO divisor.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[aj: Minor style cleanup]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20190710141009.20651-1-andrew@aj.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Joel Stanley 2019-07-10 23:40:09 +09:30 • committed by Stephen Boyd

parent 5f9e832c13

commit ebd5f82d32

1 changed files with 8 additions and 3 deletions

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drivers/clk/clk-aspeed.c

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