RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing

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Smcdeleg extension allows the M-mode to delegate selected counters
to S-mode so that it can access those counters and correpsonding
hpmevent CSRs without M-mode.

Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level
extension, ‘ccfg’ for Counter Configuration) provides access to
delegated counters and new supervisor-level state.

This patch just enables these definitions and enable parsing.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Link: https://patch.msgid.link/20260807-counter_delegation-v9-9-58658104e487@meta.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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Atish Patra 2026-08-07 19:24:32 -06:00 • committed by Paul Walmsley

parent 05e44c11f6

commit ebdec8d2c1

2 changed files with 26 additions and 0 deletions

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2

arch/riscv/include/asm/hwcap.h

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24

arch/riscv/kernel/cpufeature.c

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